High-speed HDI designs operating around 1 GHz and beyond often run into signal integrity, EMI, and impedance control issues that don’t originate in routing, they originate in the stackup. When return paths are poorly defined, plane layers are improperly arranged, or dielectric thicknesses are chosen without impedance targets in mind, even clean routing can produce reflections, excessive emissions, and degraded edge fidelity.
It’s easy to assume that routing rules alone will solve these problems. But signal behavior at these frequencies is governed by transmission line effects, return current continuity, inter-plane coupling, and material properties such as permittivity and loss tangent. Edge rate and electrical length matter more than nominal clock frequency, and HDI density increases sensitivity to stackup decisions because of thinner dielectrics, microvias, and tightly coupled planes.
In this video, we examine how stackup architecture directly influences high-speed performance inside Allegro X. Using a real 10-layer HDI carrier board as an example, we walk through plane adjacency for EMI containment, dielectric selection for controlled impedance, capacitive coupling between power and ground for power integrity, and how material properties affect propagation delay and attenuation. We also demonstrate how to configure conductor layers, dielectric materials, copper weights, and electrical parameters within Allegro X so that the stackup supports the intended signal environment before routing begins.
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Disclaimer: This video may have been recorded prior to changes made to the product’s user interface, or the video may be based on an earlier release of the product. The concepts and workflows conveyed in this video still apply to the current release of the product.