The Copper Damascene Process & Chemical Mechanical Polishing (CMP) in Advanced 3D IC Chips By Dr. Imran Khan
The process sequence used by the semiconductor industry to fabricate Cu interconnects is called the “dual-damascene” process. In this process, nanoscale features including vias and trenches are first etched in a dielectric layer (typically porous SiO2) followed by deposition of a 2–3 nm thick diffusion barrier layer. Sputter-deposited tantalum nitride (TaN) is conventionally used as a Cu diffusion barrier. A thin Cu seed layer is then sputtered, followed by bottom-up Cu electroplating to achieve void-free metallization of complex nanopatterns. Finally, excess Cu plated in the field regions is polished away using chemical mechanical polishing (CMP).